TSMC Focuses on Power and Efficiency with New 2nm Node

The Taiwan Semiconductor Manufacturing Co. (TSMC) has just officially unveiled its 2 nm node, dubbed N2. Slated for release in 2025, the new process will introduce new manufacturing technology.

According to TSMC’s teaser, the 2nm process will either provide a pure performance boost over its predecessor or, when used at the same power levels, will be much more power efficient.


TSMC spoke at length about the new 2N technology, explaining the inner workings of its architecture. The 2N will be TSMC’s first node to use all-around-the-gate field-effect transistors (GAAFETs) and will increase the chip density on the N3E node by 1.1 times. Prior to the release of the 2N, TSMC will release 3nm chips, which were also teased at the 2022 TSMC Technology Symposium.

The 3nm node is going to come in five different tiers, and with each new release, the number of transistors will increase, increasing the performance and efficiency of the chip. Starting with the N3, TSMC will later release the N3E (Enhanced), N3P (Performance Enhanced), N3S (Density Enhanced) and finally the “Ultra-High Performance” N3X. The first 3nm chips are expected to launch in the second half of this year.

While the 3nm process is closer to us in terms of launch date, it’s the 2nm that’s slightly more interesting, even though it’s still a few years away. TSMC’s goal with the 2nm node seems to be clear – to increase performance per watt to enable both higher levels of output and efficiency. The architecture as a whole has a lot to recommend. Take the example of GAA nanosheet transistors. They have canals surrounded by gates on all sides. This will reduce leakage, but the channels can also be widened which brings a performance boost. Alternatively, the channels can be narrowed to optimize energy cost.

The N3 and N2 will offer considerable performance increases over the current N5, and all offer the choice of balancing power consumption with performance per watt. As an example (first shared by Tom’s Hardware), comparing the N3 to the N5 results in up to 15% raw performance gain and up to 30% power reduction when used at the same frequency. The N3E will take those numbers even further, up to 18% and 34%, respectively.

The TSMC brochure.

Now the N2 is where things start to get exciting. We can expect to see a performance improvement of up to 15% when operated with the same power consumption as the N3E node, and if the frequency is brought down to the levels provided by the N3E, the N2 will provide power up to 30% lower. consumption.

Where will the N2 be used? It will likely find its way into all sorts of chips, ranging from mobile system-on-chips (SoCs), advanced graphics cards, and equally advanced processors. TSMC mentioned that one of the features of the 2nm process is “chiplet integration”. This implies that many manufacturers can use the N2 to use multi-chip packages to pack even more power into their chips.

Smaller process nodes are never a bad thing. The N2, when it arrives, will deliver high performance to all sorts of hardware, including the best CPUs and GPUs, while optimizing power consumption and thermals. However, until that happens, we will have to wait. TSMC won’t begin mass production until 2025, so realistically it’s unlikely we’ll see 2nm-based devices hitting the market until 2026.

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